Power saving is a constant preoccupation, especially in portable devices with an internal source of energy, such as a rechargeable battery. Power consumption of a data processor is broadly classified as dynamic power while the processor is operating (for example with component circuits switching), and static power while it is not operating but still powered (for example non-switching steady state or transistor-off state). Static or leakage power dissipation also occurs when a circuit is operating, although for today's technologies this is small compared to the dynamic power dissipation.
Various power-saving technologies have been developed to address sources of power waste. Many are all-hardware solutions such as smaller silicon process geometries, active well biasing and auto-idle detection circuits. Other technologies address the compromise between the operating parameters of the data processor on one hand and power consumption on the other hand. One such technique is known generically under the name of Dynamic power management (DPM), which describes a system that sets the power states of its hardware modules in real time to minimize power waste, with the minimum performance needed still to meet operational requirements. DPM includes techniques such as dynamic voltage and frequency scaling (DVFS) and dynamic process and temperature compensation (DPTC) for dynamically controlling operational modes, and idle time prediction for controlling low-power idle modes (such as doze, where the processor is powered but not clocked, and sleep, where some modules of the processor are not supplied with operational power).
These techniques will now be reviewed in more detail. Application programs and other system software are monitored during execution in the data processor. Some of these applications can identify their coming performance-power needs (“power aware” software) but many others cannot. Awareness of coming performance-power needs can be used to control a power manager that drives the hardware power-saving mechanisms using software drivers and power handlers in the data processor operating system.
One dynamic power saving technique is to slow or disable the clock to a logic circuit when the circuit is idling. Clock gating or clock freezing saves power not just in the registers whose clock is gated off, but also in combinational logic circuits connected to them, as the register signals are no longer propagated. Clock gating is very quick to turn on and off, so software that uses such circuits should not be affected if it is timed correctly. Static or leakage power dissipation needs more drastic measures. One solution, called power gating, is to power off the device or subcomponent. Power gating reduces both dynamic and leakage power, and can be implemented either locally on-chip or externally at the power supply unit.
Another power-saving technique is to vary the supply voltage to a circuit either when no performance is required (idling) or when variable performance is required. During idling mode the hardware can switch automatically from a higher to a lower voltage when the device or subcomponent transitions from an active state to a low-performance state. An example is a processor core design where operating voltage is reduced automatically when it enters a sleep or stop mode. Although the core is not clocked in this mode, it still suffers steady-state current leakage. Because the core does not need to execute instructions or other functions, the operating voltage can be lowered to a value just sufficient to ensure that internal state data is retained correctly. This is sometimes called stop mode voltage scaling.
The non-idling situation, where variable performance is needed, is addressed by varying the operating frequency, the operating voltage, or both. Dynamic Frequency Scaling relies on the observation that dynamic power consumption in an integrated circuit is roughly proportional to operating frequency. It makes sense, therefore, to lower the clock frequency of a processor to the lowest value that still meets the required processing performance. This means that although the software runs more slowly, it still meets its real-time deadlines with acceptable margins. This is done dynamically and needs power management software adapted to decide which frequency setting is acceptable. Better power savings can be achieved if the operating voltage is also scaled. Since power varies with the square of voltage, square-law power savings potentially are possible with voltage scaling. If voltage scaling and frequency scaling are both used, the combination, called dynamic voltage and frequency scaling (DVFS), can yield power savings roughly proportional to the cube of operating voltage.
These square-law and cube-law power savings depend not only on the configuration and efficiency of the voltage control circuits, but also on the efficiency of prediction software used to set the voltage/frequency settings. For a given integrated circuit design, the operating voltage determines the maximum usable operating frequency. The voltage (and hence frequency) are scaled to trade required performance against minimal power waste. When scaling the voltage up or down (thereby consuming more or less power), the operating frequency is also scaled, and with it the available performance of the device, which is to be controlled to remain within the operational tolerance of the design. DVFS technology addresses varying but continuing software workloads.
Performance-prediction and performance-setting algorithms are available to control the performance-power states of the system hardware such as the processor speed-voltage levels dynamically, both for run modes and for idle modes. Algorithms exist for use with DVFS-based processors that set the processor's operating frequency and voltage based on predicting the short-term software workload on the processor. An example algorithm in this class tracks the history of the recent software workload of each task (that is to say a set of program instructions that is loaded in memory) running in the OS and extrapolates it to derive a prediction of required performance in the next coming period. This technique assumes a reasonable correlation between the recent past workload of a task and that of the near future. The task status information is supplied by the OS kernel. The algorithm maintains estimates of workload and unused idling time to predict the aggregate workload (for all tasks). This normalized MCU processing level is translated by associated software into the relevant frequency and voltage settings required for the specific DVFS mechanism used. The algorithm continuously re-calculates and supplies new predictions in response to changing software workloads. In principle, the algorithm predicts the required processor performance that just meets individual deadlines for each OS task. The algorithm works reasonably well for OS tasks whose workloads don't change very rapidly.
The actual performances and power savings achieved by this kind of algorithm have been disappointing compared to theoretical calculations and prototype simulations. It is an object of the present invention to improve the achievable performances and power savings of a data processor.